1. Field of the Invention
The present invention generally relates to programmable logic devices, and more particularly, to a programmable logic device having Look Up Tables using a tri-state driver stage to improve speed, reduce power consumption, and reduce area layout compared to conventional Look Up Tables using muxes.
2. Description of Related Art
A Programmable Logic Device (PLD) is a semiconductor integrated circuit that contains fixed logic circuitry that can be programmed to perform a host of logic functions. In the semiconductor industry, PLDs are becoming increasingly popular for a number of reasons. Due to the advances of chip manufacturing technology, application specific integrated circuits (ASICs) designs have become incredibly complex. This complexity not only adds to design costs, but also the duration of time needed to develop an application specific design. To compound this problem, product life cycles are shrinking rapidly. As a result, it is often not feasible for original equipment manufacturers (OEMs) to design and use ASICs. OEMs are therefore relying more and more on PLDs. The same advances in fabrication technology have also resulted in PLDs with improved density and speed performance. Sophisticated programming software enables complex logic functions to be rapidly developed for PLDs. Furthermore, logic designs generally can also be easily migrated from one generation of PLDs to the next, further reducing product development times. The closing of the price-performance gap with ASICs and reduced product development times makes the use of PLDs compelling for many OEMs.
Most PLDs contain a two-dimensional row and column based architecture to implement custom logic. A series of row and column interconnects, typically of varying length and speed, provide signal and clock interconnects between blocks of logic on the PLD. PLDs also include basic logic elements for implementing user defined logic functions, often referred to in the industry by such names as Logic Elements (LEs), Adaptive Logic Modules (ALMs), or Complex Logic Blocks (CLBs). The basic logic elements, regardless of what they are called, usually include one or more Look Up Table (LUTs), registers for generating registered logic outputs, adders and other circuitry to implement various logic and arithmetic functions. For the purposes of the present invention, the term Logic Element as used herein, unless otherwise specified, shall mean a generic logic element, including but not limited to ALMs, CLBs, and LEs.
The Look Up Table used in most commercially available PLDs is a 16:1 mux. Four select inputs are applied to a plurality of two to one (2:1) muxes to select one of possible sixteen (1:16) possible configuration RAM bit inputs. The 2:1 muxes are typically organized into four stages in a cascaded, tree structure. In the first stage, the contents of the 16 configuration RAM bits are connected to the inputs of a first set of eight 2:1 muxes. In the second stage, four 2:1 muxes are configured to receive the outputs of the first stage muxes respectively. Similarly, in the third stage, two 2:1 muxes receive the outputs of the four muxes of the previous stage. Finally in the fourth stage, one 2:1 mux is coupled to receive the outputs of the two muxes of the third stage. Four select signals A, B, C and D are coupled to each of the muxes in the four stages respectively. The first, second, third and forth select signals A, B, C and D are used to select (8 of 16), (4 of 8), (2 of 4) and (1 of 2) inputs provided to the first, second, third and fourth muxing stages respectively. By programming the contents of the 16 configuration RAM bits, various logic functions can be implemented in the Look Up Table.
In the semiconductor industry, there is a continuous drive to improve chip fabrication technology. With each new generation of fabrication technology, the device and feature size of the components used to implement the integrated circuitry on a die, such as transistors and interconnect, become smaller and smaller. While the smaller geometries are generally desirable because they allow greater circuit functionality to be designed and implemented on a die of a given size, there are some undesirable drawbacks. For example, as device geometries become smaller and smaller, transistors tend to “leak” current. In other words, transistors conduct current even when they are supposed to be tuned-off and non-conductive.
This issue, commonly referred to as “sub-threshold leakage”, is problematic for several reasons. The sub-threshold leakage of a large number of transistors on the chip increases power consumption. The increased power consumption causes the chip to run hot. This heat may degrade the performance, or in severe situations, may cause the chip to operate improperly or outside of specifications. In some situations, a heat sink may be needed to mitigate the problem. The additional power consumption may also be a problem if the chip is used in a battery power device.
A Programmable Logic Device having Look Up Tables using a tri-state driver stage to improved speed, reduced power consumption and area compared to conventional Look Up Tables using muxes is therefore needed.